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1 Ergebnisse
1
Reducing Reversible Circuit Line Count Using Boolean Techni..:
, In:
2023 3rd International Scientific Conference of Engineering Sciences (ISCES)
,
Al-Wardi, Zaid
- p. 42-47 , 2023
Link:
https://doi.org/10.1109/ISCES58193.2023.10311466
RT T1 <cTitle>2023 3rd International Scientific Conference of Engineering Sciences (ISCES)</cTitle>: T1 <Title>Reducing Reversible Circuit Line Count Using Boolean Techniques</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10311466&Exemplar=1&LAN=DE A1 Al-Wardi, Zaid YR 2023 K1 Quantum computing K1 Costs K1 Systematics K1 Logic circuits K1 Logic gates K1 Complexity theory K1 Circuit synthesis K1 Reversible Circuits K1 Line Count Reduction K1 Boolean Techniques K1 Gate Cost K1 Hierarchical Approach K1 Function Decomposition SP 42 OP 47 LK http://dx.doi.org/https://doi.org/10.1109/ISCES58193.2023.10311466 DO https://doi.org/10.1109/ISCES58193.2023.10311466 SF ELIB - SuUB Bremen
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