I agree that this site is using cookies. You can find further informations
here
.
X
Login
Merkliste (
0
)
Home
About us
Home About us
Our history
Profile
Press & public relations
Friends
The library in figures
Exhibitions
Projects
Training, internships, careers
Films
Services & Information
Home Services & Information
Lending and interlibrary loans
Returns and renewals
Training and library tours
My Account
Library cards
New to the library?
Download Information
Opening hours
Learning spaces
PC, WLAN, copy, scan and print
Catalogs and collections
Home Catalogs and Collections
Rare books and manuscripts
Digital collections
Subject Areas
Our sites
Home Our sites
Central Library
Law Library (Juridicum)
BB Business and Economics (BB11)
BB Physics and Electrical Engineering
TB Engineering and Social Sciences
TB Economics and Nautical Sciences
TB Music
TB Art & Design
TB Bremerhaven
Contact the library
Home Contact the library
Staff Directory
Open access & publishing
Home Open access & publishing
Reference management: Citavi & RefWorks
Publishing documents
Open Access in Bremen
zur Desktop-Version
Toggle navigation
Merkliste
1 Ergebnisse
1
Mixed-Level Design Methodology With SystemVerilog Behavior ..:
, In:
2023 IEEE 12th Global Conference on Consumer Electronics (GCCE)
,
Yeh, Wei-Ting
;
Chang, Chung-Lun
;
Yin, Shang-Chih
. - p. 1172-1175 , 2023
Link:
https://doi.org/10.1109/GCCE59613.2023.10315270
RT T1 <cTitle>2023 IEEE 12th Global Conference on Consumer Electronics (GCCE)</cTitle>: T1 <Title>Mixed-Level Design Methodology With SystemVerilog Behavior Models for Digitally Controlled Power Converter ICs</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10315270&Exemplar=1&LAN=DE A1 Yeh, Wei-Ting A1 Chang, Chung-Lun A1 Yin, Shang-Chih A1 Tsai, Chien-Hung YR 2023 SN 2693-0854 K1 Semiconductor device modeling K1 Fabrication K1 Buck converters K1 Design methodology K1 Behavioral sciences K1 CMOS integrated circuits K1 Integrated circuit modeling K1 buck converter K1 digital control K1 SystemVerilog K1 behavior model K1 mixed-level design methodology SP 1172 OP 1175 LK http://dx.doi.org/https://doi.org/10.1109/GCCE59613.2023.10315270 DO https://doi.org/10.1109/GCCE59613.2023.10315270 SF ELIB - SuUB Bremen
Export
RefWorks (nur Desktop-Version!)
Flow
(Zuerst in
Flow
einloggen, dann importieren)
