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1 Ergebnisse
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PLaNe: Reverse Engineering of Planar Layouts to Gate-Level ..:
, In:
2023 IEEE Physical Assurance and Inspection of Electronics (PAINE)
,
Putz, Maximilian
;
Ludwig, Matthias
;
Lippmann, Bernhard
. - p. 1-7 , 2023
Link:
https://doi.org/10.1109/PAINE58317.2023.10317962
RT T1 <cTitle>2023 IEEE Physical Assurance and Inspection of Electronics (PAINE)</cTitle>: T1 <Title>PLaNe: Reverse Engineering of Planar Layouts to Gate-Level Netlists</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10317962&Exemplar=1&LAN=DE A1 Putz, Maximilian A1 Ludwig, Matthias A1 Lippmann, Bernhard A1 Graeb, Helmut YR 2023 K1 Electric potential K1 Layout K1 Reverse engineering K1 Logic gates K1 Semiconductor device manufacture K1 Libraries K1 Silicon K1 graph isomorphism K1 graph clustering K1 layout K1 gate-level netlist SP 1 OP 7 LK http://dx.doi.org/https://doi.org/10.1109/PAINE58317.2023.10317962 DO https://doi.org/10.1109/PAINE58317.2023.10317962 SF ELIB - SuUB Bremen
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