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An Assessment of Sample Preparation Challenges in 3D Stacke..:
, In:
2023 IEEE Physical Assurance and Inspection of Electronics (PAINE)
,
Padro, Noah
;
Patel, Yash
;
Scholl, Jon
... - p. 1-7 , 2023
Link:
https://doi.org/10.1109/PAINE58317.2023.10317984
RT T1 <cTitle>2023 IEEE Physical Assurance and Inspection of Electronics (PAINE)</cTitle>: T1 <Title>An Assessment of Sample Preparation Challenges in 3D Stacked Integrated Circuit Devices for Post-Silicon Verification and Validation</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10317984&Exemplar=1&LAN=DE A1 Padro, Noah A1 Patel, Yash A1 Scholl, Jon A1 Kelley, John A1 Waite, Adam R. A1 Sale, Matt A1 Kimura, Adam YR 2023 K1 Integrated circuits K1 Three-dimensional displays K1 Stacking K1 Milling K1 Packaging K1 Silicon K1 Dielectrics K1 delayering K1 verification K1 validation K1 trust K1 assurance K1 heterogeneous integration K1 sample preparation K1 microelectronics K1 advanced packaging SP 1 OP 7 LK http://dx.doi.org/https://doi.org/10.1109/PAINE58317.2023.10317984 DO https://doi.org/10.1109/PAINE58317.2023.10317984 SF ELIB - SuUB Bremen
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