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1
A Many-core Architecture for an Ensemble Ternary Neural Net..:
, In:
2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)
,
Kayanoma, Ryota
;
Jinguji, Akira
;
Nakahara, Hiroki
- p. 446-453 , 2023
Link:
https://doi.org/10.1109/MCSoC60832.2023.00073
RT T1 <cTitle>2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)</cTitle>: T1 <Title>A Many-core Architecture for an Ensemble Ternary Neural Network Toward High-Throughput Inference</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10387862&Exemplar=1&LAN=DE A1 Kayanoma, Ryota A1 Jinguji, Akira A1 Nakahara, Hiroki YR 2023 SN 2771-3075 K1 Data centers K1 Neural networks K1 Graphics processing units K1 Throughput K1 Table lookup K1 Central Processing Unit K1 Combinational circuits K1 Many core K1 Neural Network K1 Ensemble nueral network K1 FPGA SP 446 OP 453 LK http://dx.doi.org/https://doi.org/10.1109/MCSoC60832.2023.00073 DO https://doi.org/10.1109/MCSoC60832.2023.00073 SF ELIB - SuUB Bremen
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