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1
Design and Implementation of 32-bit Signed Divider for VLSI..:
, In:
2023 7th International Conference on Electronics, Communication and Aerospace Technology (ICECA)
,
Saravanan, M
;
Balasuriya, K A
;
Raj, D Deepak
... - p. 316-320 , 2023
Link:
https://doi.org/10.1109/ICECA58529.2023.10395698
RT T1 <cTitle>2023 7th International Conference on Electronics, Communication and Aerospace Technology (ICECA)</cTitle>: T1 <Title>Design and Implementation of 32-bit Signed Divider for VLSI Applications</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10395698&Exemplar=1&LAN=DE A1 Saravanan, M A1 Balasuriya, K A A1 Raj, D Deepak A1 Dharun, B A1 Kumar, R Dinesh A1 Naveen, Palanichamy YR 2023 K1 Performance evaluation K1 Power demand K1 Simulation K1 Very large scale integration K1 Energy efficiency K1 Hardware design languages K1 Physical design K1 32-bit divider K1 signed divider K1 Register transfer logic (RTL) K1 Arithmetic logic Unit (ALU) K1 physical design K1 floorplan K1 RTL simulation SP 316 OP 320 LK http://dx.doi.org/https://doi.org/10.1109/ICECA58529.2023.10395698 DO https://doi.org/10.1109/ICECA58529.2023.10395698 SF ELIB - SuUB Bremen
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