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1 Ergebnisse
1
Multi-Stripline Redistribution Layer Interposer Channel Des..:
, In:
2023 20th International SoC Design Conference (ISOCC)
,
Yoon, Jiwon
;
Kim, Hyunwoo
;
Sim, Boogyo
... - p. 247-248 , 2023
Link:
https://doi.org/10.1109/ISOCC59558.2023.10396127
RT T1 <cTitle>2023 20th International SoC Design Conference (ISOCC)</cTitle>: T1 <Title>Multi-Stripline Redistribution Layer Interposer Channel Design for High Bandwidth Memory Module Considering Via Interconnect</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10396127&Exemplar=1&LAN=DE A1 Yoon, Jiwon A1 Kim, Hyunwoo A1 Sim, Boogyo A1 Park, Hyunwook A1 Kim, Yigyeong A1 Park, Sujin A1 Kwon, Youngsu A1 Kim, Joungho YR 2023 SN 2472-9655 K1 Timing jitter K1 Stripline K1 Simulation K1 Crosstalk K1 Insertion loss K1 Bandwidth K1 Memory modules K1 high bandwidth memory K1 redistribution layer interposer K1 signal integrity SP 247 OP 248 LK http://dx.doi.org/https://doi.org/10.1109/ISOCC59558.2023.10396127 DO https://doi.org/10.1109/ISOCC59558.2023.10396127 SF ELIB - SuUB Bremen
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