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1 Ergebnisse
1
Optimizing Wirelength And Delay of FPGA Tile through Floorp..:
, In:
2023 IEEE 15th International Conference on ASIC (ASICON)
,
Long, Honghong
;
Bai, Yu
;
Li, Yanze
.. - p. 1-4 , 2023
Link:
https://doi.org/10.1109/ASICON58565.2023.10396538
RT T1 <cTitle>2023 IEEE 15th International Conference on ASIC (ASICON)</cTitle>: T1 <Title>Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10396538&Exemplar=1&LAN=DE A1 Long, Honghong A1 Bai, Yu A1 Li, Yanze A1 Wang, Jian A1 Lai, Jinmei YR 2023 SN 2162-755X K1 Circuit optimization K1 Integrated circuit interconnections K1 Simulated annealing K1 Delays K1 Field programmable gate arrays K1 Optimization K1 Load modeling K1 simulated annealing algorithm K1 FPGA circuit optimization K1 FPGA tile floorplan K1 Half-Perimeter Wirelength SP 1 OP 4 LK http://dx.doi.org/https://doi.org/10.1109/ASICON58565.2023.10396538 DO https://doi.org/10.1109/ASICON58565.2023.10396538 SF ELIB - SuUB Bremen
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