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1 Ergebnisse
1
PLL-SAR: A New High-Speed Analog to Digital Converter Archi..:
, In:
2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)
,
Vesely, Vladimir
;
Lee, Calvin Yoji
;
Anand, Tejasvi
. - p. 84-88 , 2023
Link:
https://doi.org/10.1109/MWSCAS57524.2023.10405967
RT T1 <cTitle>2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)</cTitle>: T1 <Title>PLL-SAR: A New High-Speed Analog to Digital Converter Architecture</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10405967&Exemplar=1&LAN=DE A1 Vesely, Vladimir A1 Lee, Calvin Yoji A1 Anand, Tejasvi A1 Moon, Un-Ku YR 2023 SN 1558-3899 K1 Power demand K1 Voltage-controlled oscillators K1 Linearity K1 Bandwidth K1 Topology K1 Registers K1 Phase locked loops K1 Time Domain K1 SAR K1 Phase-Locked Loop K1 ADC K1 VCO SP 84 OP 88 LK http://dx.doi.org/https://doi.org/10.1109/MWSCAS57524.2023.10405967 DO https://doi.org/10.1109/MWSCAS57524.2023.10405967 SF ELIB - SuUB Bremen
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