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1 Ergebnisse
1
An Optimized Vector Digital Signal Processor for 5G Achievi..:
, In:
2024 IEEE/SICE International Symposium on System Integration (SII)
,
Trang, D.T.T.
;
Nghia, V.V.
;
Van, N.T.
. - p. 1393-1398 , 2024
Link:
https://doi.org/10.1109/SII58957.2024.10417465
RT T1 <cTitle>2024 IEEE/SICE International Symposium on System Integration (SII)</cTitle>: T1 <Title>An Optimized Vector Digital Signal Processor for 5G Achieving 0.3ms Channel Estimation time for 8RX 100MHz Bandwidth</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10417465&Exemplar=1&LAN=DE A1 Trang, D.T.T. A1 Nghia, V.V. A1 Van, N.T. A1 Huy, D.X. YR 2024 SN 2474-2325 K1 Digital signal processors K1 Channel estimation K1 Signal processing algorithms K1 Computer architecture K1 Parallel processing K1 Hardware K1 Software SP 1393 OP 1398 LK http://dx.doi.org/https://doi.org/10.1109/SII58957.2024.10417465 DO https://doi.org/10.1109/SII58957.2024.10417465 SF ELIB - SuUB Bremen
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