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1 Ergebnisse
1
Design and Implementation of Optimized Based 32-Bit Arithme..:
, In:
2023 Global Conference on Information Technologies and Communications (GCITC)
,
Brahmaiah, V. Priyanka
;
Sirisinagandla, Yadagiri
;
Mouktika, B.Veda
. - p. 1-6 , 2023
Link:
https://doi.org/10.1109/GCITC60406.2023.10425953
RT T1 <cTitle>2023 Global Conference on Information Technologies and Communications (GCITC)</cTitle>: T1 <Title>Design and Implementation of Optimized Based 32-Bit Arithmetic and Logical Unit</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10425953&Exemplar=1&LAN=DE A1 Brahmaiah, V. Priyanka A1 Sirisinagandla, Yadagiri A1 Mouktika, B.Veda A1 Sai, Y. Padma YR 2023 K1 Power demand K1 Microprocessors K1 Logic gates K1 Central Processing Unit K1 Transistors K1 Arithmetic K1 Propagation delay K1 central processing unit(cpu) K1 arithmetic and logical unit K1 power dissipation K1 delay SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/GCITC60406.2023.10425953 DO https://doi.org/10.1109/GCITC60406.2023.10425953 SF ELIB - SuUB Bremen
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