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1 Ergebnisse
1
Design and Validation of Domino CMOS D Flip Flop at 16nm Re..:
, In:
2023 3rd International Conference on Advancement in Electronics & Communication Engineering (AECE)
,
Kishore, Pinninti
;
Kacharla, Sanjay
;
Kumari, Ch. Raja
- p. 440-444 , 2023
Link:
https://doi.org/10.1109/AECE59614.2023.10428357
RT T1
2023 3rd International Conference on Advancement in Electronics & Communication Engineering (AECE)
: T1
Design and Validation of Domino CMOS D Flip Flop at 16nm Regime
UL https://suche.suub.uni-bremen.de/peid=ieee-10428357&Exemplar=1&LAN=DE A1 Kishore, Pinninti A1 Kacharla, Sanjay A1 Kumari, Ch. Raja YR 2023 K1 Semiconductor device modeling K1 Power demand K1 Simulation K1 Logic gates K1 Shift registers K1 Transistors K1 MOS devices K1 domino logic K1 nanotechnology K1 low power dissipation K1 scaling K1 high performance SP 440 OP 444 LK http://dx.doi.org/https://doi.org/10.1109/AECE59614.2023.10428357 DO https://doi.org/10.1109/AECE59614.2023.10428357 SF ELIB - SuUB Bremen
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