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1 Ergebnisse
1
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider an..:
, In:
2024 IEEE International Solid-State Circuits Conference (ISSCC)
,
Xu, Dingxin
;
Liu, Zezheng
;
Kuai, Yifeng
... - p. 192-194 , 2024
Link:
https://doi.org/10.1109/ISSCC49657.2024.10454284
RT T1 <cTitle>2024 IEEE International Solid-State Circuits Conference (ISSCC)</cTitle>: T1 <Title>10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10454284&Exemplar=1&LAN=DE A1 Xu, Dingxin A1 Liu, Zezheng A1 Kuai, Yifeng A1 Huang, Hongye A1 Zhang, Yuncheng A1 Sun, Zheng A1 Liu, Bangan A1 Wang, Wenqian A1 Xiong, Yuang A1 Qiu, Junjun A1 Madany, Waleed A1 Zhang, Yi A1 Fadila, Ashbir Aviat A1 Shirane, Atsushi A1 Okada, Kenichi YR 2024 SN 2376-8606 K1 Wireless communication K1 Quantization (signal) K1 Limiting K1 Radar K1 Detectors K1 Jitter K1 Delta-sigma modulation SP 192 OP 194 LK http://dx.doi.org/https://doi.org/10.1109/ISSCC49657.2024.10454284 DO https://doi.org/10.1109/ISSCC49657.2024.10454284 SF ELIB - SuUB Bremen
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