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13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with..:

, In: 2024 IEEE International Solid-State Circuits Conference (ISSCC),

Seo, Yangho ; Choi, Jihee ; Cho, Sunki... - p. 246-248 , 2024

Link: https://doi.org/10.1109/ISSCC49657.2024.10454381

RT 
T1 <cTitle>2024 IEEE International Solid-State Circuits Conference (ISSCC)</cTitle>: T1 <Title>13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction</Title>

UL https://suche.suub.uni-bremen.de/peid=ieee-10454381&Exemplar=1&LAN=DE
				
A1 Seo, Yangho
A1 Choi, Jihee
A1 Cho, Sunki
A1 Han, Hyunwook
A1 Kim, Wonjong
A1 Ryu, Gyeongha
A1 Ahn, Jungil
A1 Cho, Younga
A1 Choi, Sungphil
A1 Lee, Seohee
A1 Lee, Wooju
A1 Lee, Chaehyuk
A1 Kim, Kiup
A1 Lee, Seongseop
A1 Park, Sangbeom
A1 Choi, Minjun
A1 Lee, Sungwoo
A1 Kim, Mino
A1 Shin, Taekyun
A1 Jeong, Hyeongsoo
A1 Kim, Hyunseung
A1 Song, Houk
A1 Hong, Yunsuk
A1 Yoon, Seokju
A1 Park, Giwook
A1 You, Hokeun
A1 Choi, Changkyu
A1 Jung, Hae-Kang
A1 Cho, Joohwan
A1 Kim, Jonghwan
YR 2024
SN 2376-8606
K1 Industries
K1 Power demand
K1 Random access memory
K1 Receivers
K1 Voltage
K1 Decision feedback equalizers
K1 Solid state circuits
SP 246
OP 248
LK http://dx.doi.org/https://doi.org/10.1109/ISSCC49657.2024.10454381
DO https://doi.org/10.1109/ISSCC49657.2024.10454381
SF ELIB - SuUB Bremen

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