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1 Ergebnisse
1
15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-..:
, In:
2024 IEEE International Solid-State Circuits Conference (ISSCC)
,
Kim, Daeyeon
;
Kim, Yusung
;
Shrivastava, Ayush
... - p. 278-280 , 2024
Link:
https://doi.org/10.1109/ISSCC49657.2024.10454501
RT T1 <cTitle>2024 IEEE International Solid-State Circuits Conference (ISSCC)</cTitle>: T1 <Title>15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10454501&Exemplar=1&LAN=DE A1 Kim, Daeyeon A1 Kim, Yusung A1 Shrivastava, Ayush A1 Park, Gyusung A1 Pillai, Anandkumar Mahadevan A1 Bannore, Kunal A1 Doan, Tri A1 Rahman, Muktadir A1 Baek, Gwanghyeon A1 Ong, Clifford A1 Wang, Xiaofei A1 Guo, Zheng A1 Karl, Eric YR 2024 SN 2376-8606 K1 Technological innovation K1 Memory management K1 Random access memory K1 Integrated circuit interconnections K1 Silicon K1 Logic design K1 Solid state circuits SP 278 OP 280 LK http://dx.doi.org/https://doi.org/10.1109/ISSCC49657.2024.10454501 DO https://doi.org/10.1109/ISSCC49657.2024.10454501 SF ELIB - SuUB Bremen
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