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34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-D..:

, In: 2024 IEEE International Solid-State Circuits Conference (ISSCC),

Fujiwara, Hidehiro ; Mori, Haruki ; Zhao, Wei-Chang... - p. 572-574 , 2024

Link: https://doi.org/10.1109/ISSCC49657.2024.10454556

RT 
T1 <cTitle>2024 IEEE International Solid-State Circuits Conference (ISSCC)</cTitle>: T1 <Title>34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell</Title>

UL https://suche.suub.uni-bremen.de/peid=ieee-10454556&Exemplar=1&LAN=DE
				
A1 Fujiwara, Hidehiro
A1 Mori, Haruki
A1 Zhao, Wei-Chang
A1 Khare, Kinshuk
A1 Lee, Cheng-En
A1 Peng, Xiaochen
A1 Joshi, Vineet
A1 Chuang, Chao-Kai
A1 Hsu, Shu-Huan
A1 Hashizume, Takeshi
A1 Naganuma, Toshiaki
A1 Tien, Chen-Hung
A1 Liu, Yao-Yi
A1 Lai, Yen-Chien
A1 Lee, Chia-Fu
A1 Chou, Tan-Li
A1 Akarvardar, Kerem
A1 Adham, Saman
A1 Wang, Yih
A1 Chih, Yu-Der
A1 Chen, Yen-Huei
A1 Liao, Hung-Jen
A1 Chang, Tsung-Yung Jonathan
YR 2024
SN 2376-8606
K1 Power demand
K1 Random access memory
K1 Voltage
K1 Computer architecture
K1 In-memory computing
K1 Throughput
K1 Foundries
SP 572
OP 574
LK http://dx.doi.org/https://doi.org/10.1109/ISSCC49657.2024.10454556
DO https://doi.org/10.1109/ISSCC49657.2024.10454556
SF ELIB - SuUB Bremen

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