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1 Ergebnisse
1
Speed-Area-Power Efficient Ternary Logic Gate Implementatio..:
, In:
2024 International Conference on Electronics, Information, and Communication (ICEIC)
,
Jeon, Gihyeon
;
Park, Daejin
- p. 1-2 , 2024
Link:
https://doi.org/10.1109/ICEIC61013.2024.10457139
RT T1
2024 International Conference on Electronics, Information, and Communication (ICEIC)
: T1
Speed-Area-Power Efficient Ternary Logic Gate Implementation Based on Typical MOS Transistors
UL https://suche.suub.uni-bremen.de/peid=ieee-10457139&Exemplar=1&LAN=DE A1 Jeon, Gihyeon A1 Park, Daejin YR 2024 SN 2767-7699 K1 Energy consumption K1 MOSFET K1 Logic gates K1 Multivalued logic K1 SPICE K1 Hardware design languages K1 Adders K1 ternary logic gates K1 ternary ripple carry adder K1 speed K1 power(energy) consumption K1 area SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.1109/ICEIC61013.2024.10457139 DO https://doi.org/10.1109/ICEIC61013.2024.10457139 SF ELIB - SuUB Bremen
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