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1 Ergebnisse
1
A Memory Efficient Run-time Re-configurable Convolution IP ..:
, In:
2023 IEEE International Symposium on Smart Electronic Systems (iSES)
,
Swati
;
Sadhukhan, Ranajoy
;
Nagar, Mitul S
. - p. 409-412 , 2023
Link:
https://doi.org/10.1109/iSES58672.2023.00091
RT T1 <cTitle>2023 IEEE International Symposium on Smart Electronic Systems (iSES)</cTitle>: T1 <Title>A Memory Efficient Run-time Re-configurable Convolution IP Core for Deep Neural Networks Inference on FPGA Devices</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10467119&Exemplar=1&LAN=DE A1 Swati A1 Sadhukhan, Ranajoy A1 Nagar, Mitul S A1 Engineer, Pinalkumar YR 2023 SN 2832-3602 K1 Performance evaluation K1 Memory management K1 Feature extraction K1 Convolutional neural networks K1 IP networks K1 Resource management K1 Dimensionality reduction K1 Design methodology K1 Computer vision K1 Computer architecture K1 Runtime environment K1 Table lookup K1 Power demand K1 convolutional neural network K1 re-configurable K1 high-level synthesis K1 FPGA K1 multiply-accumulate SP 409 OP 412 LK http://dx.doi.org/https://doi.org/10.1109/iSES58672.2023.00091 DO https://doi.org/10.1109/iSES58672.2023.00091 SF ELIB - SuUB Bremen
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