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1 Ergebnisse
1
Accelerating Sorting Performance on FPGA: Combining Quick S..:
, In:
2023 IEEE International Symposium on Smart Electronic Systems (iSES)
,
Kumar Reddy, B. Naresh
;
K, Sarangam
;
Dandeliya, Sushmita
.. - p. 405-408 , 2023
Link:
https://doi.org/10.1109/iSES58672.2023.00090
RT T1
2023 IEEE International Symposium on Smart Electronic Systems (iSES)
: T1
Accelerating Sorting Performance on FPGA: Combining Quick Sort and Heap Sort through Hybrid Pipelining
UL https://suche.suub.uni-bremen.de/peid=ieee-10467123&Exemplar=1&LAN=DE A1 Kumar Reddy, B. Naresh A1 K, Sarangam A1 Dandeliya, Sushmita A1 Sai Naidu, S. Pavan A1 P, Naveen Kumar YR 2023 SN 2832-3602 K1 Throughput K1 Hardware K1 Resource management K1 Low latency communication K1 Field programmable gate arrays K1 Faces K1 Sorting K1 Quick sort K1 Heap-based sort K1 FPGA K1 Latency SP 405 OP 408 LK http://dx.doi.org/https://doi.org/10.1109/iSES58672.2023.00090 DO https://doi.org/10.1109/iSES58672.2023.00090 SF ELIB - SuUB Bremen
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