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1 Ergebnisse
1
LayNet: Layout Size Prediction for Memory Design Using Grap..:
, In:
2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)
,
Ji, Hye Rim
;
Kim, Jong Seong
;
Choi, Jung Yun
. - p. 484-490 , 2024
Link:
https://doi.org/10.1109/ASP-DAC58780.2024.10473802
RT T1 <cTitle>2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)</cTitle>: T1 <Title>LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10473802&Exemplar=1&LAN=DE A1 Ji, Hye Rim A1 Kim, Jong Seong A1 Choi, Jung Yun A1 Lee, Jee Hyong YR 2024 SN 2153-697X K1 Wiring K1 Error analysis K1 Layout K1 Memory management K1 Manuals K1 Predictive models K1 Reliability engineering SP 484 OP 490 LK http://dx.doi.org/https://doi.org/10.1109/ASP-DAC58780.2024.10473802 DO https://doi.org/10.1109/ASP-DAC58780.2024.10473802 SF ELIB - SuUB Bremen
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