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1 Ergebnisse
1
A Technique to Optimize Clock Latency after CCOpt exploitin..:
, In:
2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)
,
Dhar, Abhiram
;
Nakhate, Sangeeta
;
Chelani, Vikas
.. - p. 1-5 , 2024
Link:
https://doi.org/10.1109/SCEECS61402.2024.10482032
RT T1 <cTitle>2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)</cTitle>: T1 <Title>A Technique to Optimize Clock Latency after CCOpt exploiting Useful Skew</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10482032&Exemplar=1&LAN=DE A1 Dhar, Abhiram A1 Nakhate, Sangeeta A1 Chelani, Vikas A1 Gupta, Animesh A1 Tirkey, Sukeshni YR 2024 SN 2688-0288 K1 Performance evaluation K1 Integrated circuit synthesis K1 Computer science K1 Manuals K1 Inverters K1 Delays K1 Complexity theory K1 Physical Design K1 Clock Latency K1 Insertion Delay K1 CTS K1 Useful Skew SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/SCEECS61402.2024.10482032 DO https://doi.org/10.1109/SCEECS61402.2024.10482032 SF ELIB - SuUB Bremen
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