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1 Ergebnisse
1
Design of Full Adder Circuits with Optimized Power and Spee..:
, In:
2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)
,
Rajput, Vishal
;
Singh, Abhay Pratap
;
Tirkey, Sukeshni
. - p. 1-5 , 2024
Link:
https://doi.org/10.1109/SCEECS61402.2024.10482060
RT T1 <cTitle>2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)</cTitle>: T1 <Title>Design of Full Adder Circuits with Optimized Power and Speed Using CMOS Technique</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10482060&Exemplar=1&LAN=DE A1 Rajput, Vishal A1 Singh, Abhay Pratap A1 Tirkey, Sukeshni A1 Nakhate, Sangeeta YR 2024 SN 2688-0288 K1 Power demand K1 Sensitivity K1 Fluctuations K1 Circuits K1 Very large scale integration K1 CMOS technology K1 Delays K1 Full adder (FA) K1 Cadence Virtuoso K1 Static power K1 CMOS K1 Delay K1 Low Power K1 PDP K1 Dynamic power K1 PVT SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/SCEECS61402.2024.10482060 DO https://doi.org/10.1109/SCEECS61402.2024.10482060 SF ELIB - SuUB Bremen
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