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1 Ergebnisse
1
A Novel 1-bit Fast and Low Power 17-T Full Adder Circuit:
, In:
2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)
,
Gupta, Kripi
;
Tiwari, Ravindra
;
Singh, Nikita
... - p. 1-5 , 2024
Link:
https://doi.org/10.1109/SCEECS61402.2024.10482063
RT T1 <cTitle>2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)</cTitle>: T1 <Title>A Novel 1-bit Fast and Low Power 17-T Full Adder Circuit</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10482063&Exemplar=1&LAN=DE A1 Gupta, Kripi A1 Tiwari, Ravindra A1 Singh, Nikita A1 Agrawal, Aachman A1 Singh, Abhay Pratap A1 Baghel, R. K. YR 2024 SN 2688-0288 K1 Semiconductor device modeling K1 Program processors K1 Power demand K1 Simulation K1 Stability analysis K1 Delays K1 Transistors K1 Arithmetic Logic Units (ALUs) K1 Low-Power Design K1 Hybrid Full Adder (FA) K1 XOR-XNOR circuit K1 Power- Delay Product (PDP) SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/SCEECS61402.2024.10482063 DO https://doi.org/10.1109/SCEECS61402.2024.10482063 SF ELIB - SuUB Bremen
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