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Vigil: A RISC-V SoC Architecture for 2-fold Hybrid CNN-kNN ..:
, In:
2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)
,
Bhattacharyya, Tamonash
;
Ghosal, Prasun
;
Sonam
. - p. 372-377 , 2024
Link:
https://doi.org/10.1109/VLSID60093.2024.00068
RT T1 <cTitle>2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)</cTitle>: T1 <Title>Vigil: A RISC-V SoC Architecture for 2-fold Hybrid CNN-kNN based Fall Detector Implementation on FPGA</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10483334&Exemplar=1&LAN=DE A1 Bhattacharyya, Tamonash A1 Ghosal, Prasun A1 Sonam A1 Deb, Sujay YR 2024 SN 2380-6923 K1 Heuristic algorithms K1 Computational modeling K1 Computer architecture K1 Switches K1 Very large scale integration K1 Probabilistic logic K1 Real-time systems K1 RISC-V K1 Internet-of-Things (IoT) K1 Hardware-Software Co-design K1 Edge Computing K1 FPGA K1 Fall Detection K1 Assistive Technologies K1 Hardware for AI K1 pCNN K1 CNN-kNN K1 PolarFire SoC SP 372 OP 377 LK http://dx.doi.org/https://doi.org/10.1109/VLSID60093.2024.00068 DO https://doi.org/10.1109/VLSID60093.2024.00068 SF ELIB - SuUB Bremen
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