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1
Characteristic Exploitation of Programmable Delay Line Infl..:
, In:
2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)
,
Sivaraman, R
;
Muralidaran, D
;
Muthaiah, R
. - p. 480-485 , 2024
Link:
https://doi.org/10.1109/VLSID60093.2024.00086
RT T1 <cTitle>2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)</cTitle>: T1 <Title>Characteristic Exploitation of Programmable Delay Line Influenced Oscillator Circuit as Hardware Security Primitive</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10483341&Exemplar=1&LAN=DE A1 Sivaraman, R A1 Muralidaran, D A1 Muthaiah, R A1 Sriram, V S Shankar YR 2024 SN 2380-6923 K1 VHDL K1 Hardware security K1 Jitter K1 Delay lines K1 Very large scale integration K1 Inverters K1 Vectors K1 key generation K1 Ring Oscillator K1 Inverter K1 Autocorrelation SP 480 OP 485 LK http://dx.doi.org/https://doi.org/10.1109/VLSID60093.2024.00086 DO https://doi.org/10.1109/VLSID60093.2024.00086 SF ELIB - SuUB Bremen
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