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OEDASA: Optimization Enabled Error-Diluted Approximate Syst..:
, In:
2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)
,
Devi, Dantu Nandini
;
Kumar, Gandi Ajay
;
Gowda, Bindu G
. - p. 593-598 , 2024
Link:
https://doi.org/10.1109/VLSID60093.2024.00105
RT T1
2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)
: T1
OEDASA: Optimization Enabled Error-Diluted Approximate Systolic Array Design for an Image Processing Application
UL https://suche.suub.uni-bremen.de/peid=ieee-10483416&Exemplar=1&LAN=DE A1 Devi, Dantu Nandini A1 Kumar, Gandi Ajay A1 Gowda, Bindu G A1 Rao, Madhav YR 2024 SN 2380-6923 K1 Image processing K1 Approximate computing K1 Metaheuristics K1 Computer architecture K1 Benchmark testing K1 Very large scale integration K1 Systolic arrays K1 Systolic Array K1 Convolution K1 Approximate Computing K1 Image Processing K1 Particle Swarm Optimisation (PSO) SP 593 OP 598 LK http://dx.doi.org/https://doi.org/10.1109/VLSID60093.2024.00105 DO https://doi.org/10.1109/VLSID60093.2024.00105 SF ELIB - SuUB Bremen
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