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Design of MoS2 based Inverter Circuits considering Interfac..:
, In:
2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)
,
Sarath, S
;
Manekar, Darshni
;
Shukla, Rajendra P.
. - p. 43-48 , 2024
Link:
https://doi.org/10.1109/VLSID60093.2024.00012
RT T1
2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)
: T1
Design of MoS2 based Inverter Circuits considering Interface Trap effect
UL https://suche.suub.uni-bremen.de/peid=ieee-10483435&Exemplar=1&LAN=DE A1 Sarath, S A1 Manekar, Darshni A1 Shukla, Rajendra P. A1 Yadav, Chandan YR 2024 SN 2380-6923 K1 Solid modeling K1 Analytical models K1 Inverters K1 Data models K1 Delays K1 Circuit synthesis K1 Transistors K1 Inverter K1 Compact model K1 MoS₂ FET K1 Interface Trap K1 Verilog-A SP 43 OP 48 LK http://dx.doi.org/https://doi.org/10.1109/VLSID60093.2024.00012 DO https://doi.org/10.1109/VLSID60093.2024.00012 SF ELIB - SuUB Bremen
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