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1 Ergebnisse
1
SEU/SET Evaluation of Digital VLSI Design from Register Tra..:
, In:
2023 7th International Conference on Electrical, Mechanical and Computer Engineering (ICEMCE)
,
Chen, Xin
;
Huo, Liangzhou
;
Shen, Zhihao
... - p. 438-442 , 2023
Link:
https://doi.org/10.1109/ICEMCE60359.2023.10490669
RT T1 <cTitle>2023 7th International Conference on Electrical, Mechanical and Computer Engineering (ICEMCE)</cTitle>: T1 <Title>SEU/SET Evaluation of Digital VLSI Design from Register Transfer Level to Layout Level</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10490669&Exemplar=1&LAN=DE A1 Chen, Xin A1 Huo, Liangzhou A1 Shen, Zhihao A1 Jiang, Ziyun A1 Zhang, Zhiwei A1 Zhang, Ying YR 2023 K1 Single event transients K1 Simulation K1 Single event upsets K1 Space radiation K1 Very large scale integration K1 Logic gates K1 Registers K1 single event upset (SEU) K1 single event transient (SET) K1 fault injection K1 software simulation K1 VLSI circuit SP 438 OP 442 LK http://dx.doi.org/https://doi.org/10.1109/ICEMCE60359.2023.10490669 DO https://doi.org/10.1109/ICEMCE60359.2023.10490669 SF ELIB - SuUB Bremen
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