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1
Performance Analysis of Low Power Hybrid Full Adder Using P..:
, In:
2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI)
,
Sharma, Priyank
;
Mishra, Vishwas
;
Akashe, Shyam
- p. 1-5 , 2024
Link:
https://doi.org/10.1109/IATMSI60426.2024.10503063
RT T1
2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI)
: T1
Performance Analysis of Low Power Hybrid Full Adder Using Pass Transistor Logic
UL https://suche.suub.uni-bremen.de/peid=ieee-10503063&Exemplar=1&LAN=DE A1 Sharma, Priyank A1 Mishra, Vishwas A1 Akashe, Shyam YR 2024 K1 Temperature measurement K1 Technological innovation K1 Noise K1 Very large scale integration K1 Hybrid power systems K1 Delays K1 Performance analysis K1 Hybrid full adder K1 Reliability K1 CMOS technology K1 power consumption K1 delay SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/IATMSI60426.2024.10503063 DO https://doi.org/10.1109/IATMSI60426.2024.10503063 SF ELIB - SuUB Bremen
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