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1 Ergebnisse
1
Design Implementation of FPGA-Based Neural Network Accelera..:
, In:
2024 4th International Conference on Consumer Electronics and Computer Engineering (ICCECE)
,
Zhang, Lizhao
;
Pan, Zhongliang
- p. 163-166 , 2024
Link:
https://doi.org/10.1109/ICCECE61317.2024.10504174
RT T1 <cTitle>2024 4th International Conference on Consumer Electronics and Computer Engineering (ICCECE)</cTitle>: T1 <Title>Design Implementation of FPGA-Based Neural Network Acceleration</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10504174&Exemplar=1&LAN=DE A1 Zhang, Lizhao A1 Pan, Zhongliang YR 2024 K1 YOLO K1 Analytical models K1 Accelerator architectures K1 Bandwidth K1 Writing K1 Energy efficiency K1 Delays K1 convolutional neural networks K1 YOLOv5 K1 multi-channel data transfer K1 FPGA SP 163 OP 166 LK http://dx.doi.org/https://doi.org/10.1109/ICCECE61317.2024.10504174 DO https://doi.org/10.1109/ICCECE61317.2024.10504174 SF ELIB - SuUB Bremen
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