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ABACUS: ASIP-Based Avro Schema-Customizable Parser Accelera..:
, In:
2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)
,
Hahn, Tobias
;
Schull, Daniel
;
Wildermann, Stefan
. - p. 79-85 , 2024
Link:
https://doi.org/10.1109/DDECS60919.2024.10508904
RT T1 <cTitle>2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)</cTitle>: T1 <Title>ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10508904&Exemplar=1&LAN=DE A1 Hahn, Tobias A1 Schull, Daniel A1 Wildermann, Stefan A1 Teich, Jurgen YR 2024 SN 2473-2117 K1 Instruction sets K1 Memory management K1 Loading K1 Circuits K1 Throughput K1 Big Data applications K1 Central Processing Unit K1 Avro K1 parsing K1 FPGA K1 semi-structured data K1 accelerator SP 79 OP 85 LK http://dx.doi.org/https://doi.org/10.1109/DDECS60919.2024.10508904 DO https://doi.org/10.1109/DDECS60919.2024.10508904 SF ELIB - SuUB Bremen
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