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1
TCC: GPGPU Architecture for Instruction Decoder and Control..:
, In:
2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)
,
K, Raghunandana K
;
R, Yogesh Prasad K
;
Reorda, M. Sonza
. - p. 104-109 , 2024
Link:
https://doi.org/10.1109/DDECS60919.2024.10508915
RT T1 <cTitle>2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)</cTitle>: T1 <Title>TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10508915&Exemplar=1&LAN=DE A1 K, Raghunandana K A1 R, Yogesh Prasad K A1 Reorda, M. Sonza A1 Singh, Virendra YR 2024 SN 2473-2117 K1 Microarchitecture K1 Codes K1 Simulation K1 Redundancy K1 Computer architecture K1 Programming K1 Throughput K1 GPGPU K1 Fault-tolerant K1 Redundant K1 Error Detection K1 Instruction Decoder K1 control divergence SP 104 OP 109 LK http://dx.doi.org/https://doi.org/10.1109/DDECS60919.2024.10508915 DO https://doi.org/10.1109/DDECS60919.2024.10508915 SF ELIB - SuUB Bremen
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