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1 Ergebnisse
1
Optimised AES with RISC-V Vector Extensions:
, In:
2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)
,
Rizi, Mahnaz Namazi
;
Zidaric, Nusa
;
Batina, Lejla
. - p. 57-60 , 2024
Link:
https://doi.org/10.1109/DDECS60919.2024.10508919
RT T1
2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)
: T1
Optimised AES with RISC-V Vector Extensions
UL https://suche.suub.uni-bremen.de/peid=ieee-10508919&Exemplar=1&LAN=DE A1 Rizi, Mahnaz Namazi A1 Zidaric, Nusa A1 Batina, Lejla A1 Mentens, Nele YR 2024 SN 2473-2117 K1 Computers K1 Quantum computing K1 Instruction sets K1 Standards organizations K1 Organizations K1 Vectors K1 Hardware K1 Classic McEliece K1 AES K1 Acceleration K1 RISC-V K1 Vector Extensions SP 57 OP 60 LK http://dx.doi.org/https://doi.org/10.1109/DDECS60919.2024.10508919 DO https://doi.org/10.1109/DDECS60919.2024.10508919 SF ELIB - SuUB Bremen
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