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1 Ergebnisse
1
V2Va: An Efficient Verilog-to-Verilog-A Translator for Acce..:
, In:
2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
,
Shao, Yicong
;
Wang, Chao
;
Huang, Jiajie
... - p. 222-226 , 2023
Link:
https://doi.org/10.1109/APCCAS60141.2023.00058
RT T1
2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
: T1
V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation
UL https://suche.suub.uni-bremen.de/peid=ieee-10510011&Exemplar=1&LAN=DE A1 Shao, Yicong A1 Wang, Chao A1 Huang, Jiajie A1 Lu, Wangzilu A1 Gu, Zhiwen A1 Li, Longfan A1 Zhang, Yuhang A1 Zhao, Jian A1 Mao, Wei A1 Li, Yongfu YR 2023 SN 2768-3516 K1 Circuits and systems K1 Asia K1 Syntactics K1 Circuit synthesis K1 Hardware design languages K1 Engines K1 Digital circuits K1 Verilog K1 Verilog-A K1 Mixed-signal Simulation K1 abstract syntax tree K1 translator K1 generator SP 222 OP 226 LK http://dx.doi.org/https://doi.org/10.1109/APCCAS60141.2023.00058 DO https://doi.org/10.1109/APCCAS60141.2023.00058 SF ELIB - SuUB Bremen
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