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1 Ergebnisse
1
A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipli..:
, In:
2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
,
Aizaz, Zainab
;
Khare, Kavita
;
Khan, Mohd. Anas
.. - p. 241-245 , 2023
Link:
https://doi.org/10.1109/APCCAS60141.2023.00062
RT T1 <cTitle>2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)</cTitle>: T1 <Title>A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipliers for DSP and Machine Learning Applications on FPGAs</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10510015&Exemplar=1&LAN=DE A1 Aizaz, Zainab A1 Khare, Kavita A1 Khan, Mohd. Anas A1 Singh, Mahesh Kumar A1 Vaithiyanathan, Dhandapani YR 2023 SN 2768-3516 K1 Circuits K1 Asia K1 Machine learning K1 Digital signal processing K1 Parallel processing K1 Logic gates K1 Table lookup K1 Look-up-tables K1 FPGA K1 Approximate multipliers K1 Neural Networks SP 241 OP 245 LK http://dx.doi.org/https://doi.org/10.1109/APCCAS60141.2023.00062 DO https://doi.org/10.1109/APCCAS60141.2023.00062 SF ELIB - SuUB Bremen
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