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1 Ergebnisse
1
Analysis of CMOS Full Adder Circuits for Multiplier Logic A..:
, In:
2024 International Conference on Distributed Computing and Optimization Techniques (ICDCOT)
,
Ganesh Reddy, Jyothi
;
Lokesh Krishna, K.
;
Priyanka Keerthi, Jinka
... - p. 1-5 , 2024
Link:
https://doi.org/10.1109/ICDCOT61034.2024.10515488
RT T1 <cTitle>2024 International Conference on Distributed Computing and Optimization Techniques (ICDCOT)</cTitle>: T1 <Title>Analysis of CMOS Full Adder Circuits for Multiplier Logic Architectures</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10515488&Exemplar=1&LAN=DE A1 Ganesh Reddy, Jyothi A1 Lokesh Krishna, K. A1 Priyanka Keerthi, Jinka A1 Revanth, Karamala A1 Sai Deekshitha, Kalluri A1 Doraswamy, B. YR 2024 K1 Power demand K1 Logic circuits K1 Metals K1 Computer architecture K1 Logic gates K1 Delays K1 Power dissipation K1 Full-adder K1 low power K1 signal processing system K1 transmission gate K1 CMOS and propagation delay SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ICDCOT61034.2024.10515488 DO https://doi.org/10.1109/ICDCOT61034.2024.10515488 SF ELIB - SuUB Bremen
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