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1 Ergebnisse
1
Optimization of Polysilicon Gate Etching Process in SONOS M..:
, In:
2024 Conference of Science and Technology for Integrated Circuits (CSTIC)
,
Yang, Wanli
;
Liu, Zhengming
;
Shi, Xiaoming
... - p. 1-3 , 2024
Link:
https://doi.org/10.1109/CSTIC61820.2024.10531846
RT T1 <cTitle>2024 Conference of Science and Technology for Integrated Circuits (CSTIC)</cTitle>: T1 <Title>Optimization of Polysilicon Gate Etching Process in SONOS Memory Fabrication</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10531846&Exemplar=1&LAN=DE A1 Yang, Wanli A1 Liu, Zhengming A1 Shi, Xiaoming A1 Shen, Jingru A1 Yin, Juxin A1 Zhang, Xuqing A1 Gao, Dawei YR 2024 K1 SONOS devices K1 Surface morphology K1 Process control K1 Morphology K1 Memory K1 Logic gates K1 Etching SP 1 OP 3 LK http://dx.doi.org/https://doi.org/10.1109/CSTIC61820.2024.10531846 DO https://doi.org/10.1109/CSTIC61820.2024.10531846 SF ELIB - SuUB Bremen
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