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1 Ergebnisse
1
Short-Loop Method to Shorten Gate Process Characterization ..:
, In:
2024 Conference of Science and Technology for Integrated Circuits (CSTIC)
,
Li, Bing
;
Fei, Wenwen
;
Lee, Byunghak
- p. 1-3 , 2024
Link:
https://doi.org/10.1109/CSTIC61820.2024.10531936
RT T1 <cTitle>2024 Conference of Science and Technology for Integrated Circuits (CSTIC)</cTitle>: T1 <Title>Short-Loop Method to Shorten Gate Process Characterization Cycle Time</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10531936&Exemplar=1&LAN=DE A1 Li, Bing A1 Fei, Wenwen A1 Lee, Byunghak YR 2024 K1 Performance evaluation K1 Integrated circuits K1 Costs K1 Lithography K1 Fitting K1 Logic gates K1 Time measurement K1 short-loop methodology K1 characterize Gate process K1 extract electrical parameters SP 1 OP 3 LK http://dx.doi.org/https://doi.org/10.1109/CSTIC61820.2024.10531936 DO https://doi.org/10.1109/CSTIC61820.2024.10531936 SF ELIB - SuUB Bremen
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