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1 Ergebnisse
1
Virtual FAB Semiconductor Process Modeling Augmented Vertic..:
, In:
2024 Conference of Science and Technology for Integrated Circuits (CSTIC)
,
Di, Zhaohai
;
Luo, Yanna
;
Xu, Haoqing
... - p. 1-3 , 2024
Link:
https://doi.org/10.1109/CSTIC61820.2024.10531984
RT T1 <cTitle>2024 Conference of Science and Technology for Integrated Circuits (CSTIC)</cTitle>: T1 <Title>Virtual FAB Semiconductor Process Modeling Augmented Vertical Gate All Around Complementary FET Based 6T SRAM Path-Finding</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10531984&Exemplar=1&LAN=DE A1 Di, Zhaohai A1 Luo, Yanna A1 Xu, Haoqing A1 He, Hao A1 Yin, Huaxiang A1 Wu, Zhenhua YR 2024 K1 Semiconductor device modeling K1 Logic circuits K1 Field effect transistors K1 Gallium arsenide K1 Logic gates K1 SRAM cells K1 Stability analysis SP 1 OP 3 LK http://dx.doi.org/https://doi.org/10.1109/CSTIC61820.2024.10531984 DO https://doi.org/10.1109/CSTIC61820.2024.10531984 SF ELIB - SuUB Bremen
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