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1 Ergebnisse
1
The Modeling and Optimization of Line Width Roughness in Po..:
, In:
2024 Conference of Science and Technology for Integrated Circuits (CSTIC)
,
Wang, Yaoting
;
Kong, Mengshu
;
Wu, Yongyu
.. - p. 1-3 , 2024
Link:
https://doi.org/10.1109/CSTIC61820.2024.10532005
RT T1 <cTitle>2024 Conference of Science and Technology for Integrated Circuits (CSTIC)</cTitle>: T1 <Title>The Modeling and Optimization of Line Width Roughness in Polysilicon Gate for Improving the Performance of CMOS Device</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10532005&Exemplar=1&LAN=DE A1 Wang, Yaoting A1 Kong, Mengshu A1 Wu, Yongyu A1 Gao, Dawei A1 Xu, Kai YR 2024 K1 Semiconductor device modeling K1 Performance evaluation K1 Integrated circuits K1 MOSFET K1 Logic gates K1 Electric variables K1 Data models SP 1 OP 3 LK http://dx.doi.org/https://doi.org/10.1109/CSTIC61820.2024.10532005 DO https://doi.org/10.1109/CSTIC61820.2024.10532005 SF ELIB - SuUB Bremen
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