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1 Ergebnisse
1
Logic Synthesis for XOR-AND Graphs via Reed-Muller Represen..:
, In:
2024 Conference of Science and Technology for Integrated Circuits (CSTIC)
,
Liu, Sen
;
Zhou, Hongwei
;
Xia, Yinshui
.. - p. 1-3 , 2024
Link:
https://doi.org/10.1109/CSTIC61820.2024.10532048
RT T1
2024 Conference of Science and Technology for Integrated Circuits (CSTIC)
: T1
Logic Synthesis for XOR-AND Graphs via Reed-Muller Representations
UL https://suche.suub.uni-bremen.de/peid=ieee-10532048&Exemplar=1&LAN=DE A1 Liu, Sen A1 Zhou, Hongwei A1 Xia, Yinshui A1 Wang, Lunyao A1 Chu, Zhufei YR 2024 K1 Integrated circuits K1 Quantum computing K1 Boolean functions K1 Transforms K1 Logic gates K1 Benchmark testing K1 Cryptography K1 Logic synthesis K1 XOR-AND Graph K1 Reed-Muller logic K1 area-aware optimization SP 1 OP 3 LK http://dx.doi.org/https://doi.org/10.1109/CSTIC61820.2024.10532048 DO https://doi.org/10.1109/CSTIC61820.2024.10532048 SF ELIB - SuUB Bremen
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