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1 Ergebnisse
1
Design Framework for Ferroelectric Gate Stack Engineering o..:
, In:
2024 IEEE International Memory Workshop (IMW)
,
Das, Dipjyoti
;
Fernandes, Lance
;
Ravindran, Prasanna Venkatesan
... - p. 1-4 , 2024
Link:
https://doi.org/10.1109/IMW59701.2024.10536982
RT T1
2024 IEEE International Memory Workshop (IMW)
: T1
Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation
UL https://suche.suub.uni-bremen.de/peid=ieee-10536982&Exemplar=1&LAN=DE A1 Das, Dipjyoti A1 Fernandes, Lance A1 Ravindran, Prasanna Venkatesan A1 Song, Taeyoung A1 Park, Chinsung A1 Afroze, Nashrah A1 Tian, Mengkun A1 Chen, Hang A1 Chem, Winston A1 Kim, Kijoon A1 Woo, Jongho A1 Lim, Suhwan A1 Kim, Kwangsoo A1 Kim, Wanki A1 Ha, Daewon A1 Yu, Shimeng A1 Datta, Suman A1 Khan, Asif YR 2024 SN 2573-7503 K1 Measurement K1 Electric potential K1 Design methodology K1 Focusing K1 Voltage K1 Switches K1 Logic gates SP 1 OP 4 LK http://dx.doi.org/https://doi.org/10.1109/IMW59701.2024.10536982 DO https://doi.org/10.1109/IMW59701.2024.10536982 SF ELIB - SuUB Bremen
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