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1 Ergebnisse
1
Optimization of CFET Standard Cell Using Double-Cell-Height..:
, In:
2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
,
Huang, Liang-Chi
;
Lu, Ko-Cheng
;
Kang, Wei-Cheng
... - p. 1-3 , 2024
Link:
https://doi.org/10.1109/VLSITSA60681.2024.10546339
RT T1 <cTitle>2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)</cTitle>: T1 <Title>Optimization of CFET Standard Cell Using Double-Cell-Height Structure</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10546339&Exemplar=1&LAN=DE A1 Huang, Liang-Chi A1 Lu, Ko-Cheng A1 Kang, Wei-Cheng A1 Juan, Bo-Hsun A1 Chu, Pen-Yi A1 Lu, Chih-Hsuan A1 Chang, Tzu-Hsuan YR 2024 K1 Stacking K1 Layout K1 Integrated circuit interconnections K1 Very large scale integration K1 Routing K1 Libraries K1 Transistors SP 1 OP 3 LK http://dx.doi.org/https://doi.org/10.1109/VLSITSA60681.2024.10546339 DO https://doi.org/10.1109/VLSITSA60681.2024.10546339 SF ELIB - SuUB Bremen
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