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1
On DRC Cleanness of Cell Porting for Design Migrations in F..:
, In:
2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
,
Wang, Ching-Ying
;
Chen, Chen-Ho
;
Chang, Po-Hsiang
... - p. 1-4 , 2024
Link:
https://doi.org/10.1109/VLSITSA60681.2024.10546349
RT T1
2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
: T1
On DRC Cleanness of Cell Porting for Design Migrations in Foundries and Technologies
UL https://suche.suub.uni-bremen.de/peid=ieee-10546349&Exemplar=1&LAN=DE A1 Wang, Ching-Ying A1 Chen, Chen-Ho A1 Chang, Po-Hsiang A1 Hsieh, Chien-Yu A1 Su, Ching-Feng A1 Ji, Scott A1 Liu, Chien-Nan Jimmy A1 Chen, Hung-Ming YR 2024 K1 Layout K1 Switches K1 High-voltage techniques K1 Very large scale integration K1 Libraries K1 Foundries K1 Topology K1 migration K1 cell layout K1 standard cell K1 design rules K1 corner stitch K1 constraint graph SP 1 OP 4 LK http://dx.doi.org/https://doi.org/10.1109/VLSITSA60681.2024.10546349 DO https://doi.org/10.1109/VLSITSA60681.2024.10546349 SF ELIB - SuUB Bremen
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