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1 Ergebnisse
1
A 14.7-20-Gb/s Reference-Less Baud-Rate CDR Circuit with On..:
, In:
2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
,
Chou, Po-Yuan
;
Liu, Shen-Iuan
- p. 1-4 , 2024
Link:
https://doi.org/10.1109/VLSITSA60681.2024.10546382
RT T1 <cTitle>2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)</cTitle>: T1 <Title>A 14.7-20-Gb/s Reference-Less Baud-Rate CDR Circuit with One-Tap DFE and Time-Interpolation</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10546382&Exemplar=1&LAN=DE A1 Chou, Po-Yuan A1 Liu, Shen-Iuan YR 2024 K1 Latches K1 Voltage-controlled oscillators K1 Phase frequency detectors K1 Detectors K1 Very large scale integration K1 CMOS technology K1 Decision feedback equalizers K1 Reference-less K1 baud-rate K1 clock and data recovery K1 decision feedback equalizer K1 asymmetrical K1 phase detector K1 time-interpolated latch K1 frequency acquisition SP 1 OP 4 LK http://dx.doi.org/https://doi.org/10.1109/VLSITSA60681.2024.10546382 DO https://doi.org/10.1109/VLSITSA60681.2024.10546382 SF ELIB - SuUB Bremen
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