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1 Ergebnisse
1
Design of an Efficient Deep Neural Network Accelerator Base..:
, In:
2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
,
Hsiao, Shen-Fu
;
Lin, Sin-Chen
;
Chen, Guan-Lin
... - p. 1-4 , 2024
Link:
https://doi.org/10.1109/VLSITSA60681.2024.10546390
RT T1
2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
: T1
Design of an Efficient Deep Neural Network Accelerator Based on Block Posit Number Representation
UL https://suche.suub.uni-bremen.de/peid=ieee-10546390&Exemplar=1&LAN=DE A1 Hsiao, Shen-Fu A1 Lin, Sin-Chen A1 Chen, Guan-Lin A1 Yang, Shih-Hua A1 Yuan, Yen-Che A1 Chen, Kun-Chih YR 2024 K1 Training K1 Degradation K1 Costs K1 Artificial neural networks K1 Very large scale integration K1 Hardware K1 High dynamic range K1 deep neural networks (DNN) K1 convolutional neural networks (CNN) K1 Floating model quantization K1 DNN hardware accelerators K1 multi-precision design SP 1 OP 4 LK http://dx.doi.org/https://doi.org/10.1109/VLSITSA60681.2024.10546390 DO https://doi.org/10.1109/VLSITSA60681.2024.10546390 SF ELIB - SuUB Bremen
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