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1 Ergebnisse
1
On Gate Flip Errors in Computing-In-Memory:
, In:
2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)
,
Chowdhury, Zamshed I.
;
Cilasun, Husrev
;
Resch, Salonik
... - p. 1-6 , 2024
Link:
https://doi.org/10.23919/DATE58400.2024.10546875
RT T1 <cTitle>2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)</cTitle>: T1 <Title>On Gate Flip Errors in Computing-In-Memory</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10546875&Exemplar=1&LAN=DE A1 Chowdhury, Zamshed I. A1 Cilasun, Husrev A1 Resch, Salonik A1 Zabihi, Masoud A1 Lv, Yang A1 Zink, Brandon A1 Wang, Jian-Ping A1 Sapatnekar, Sachin S. A1 Karpuzcu, Ulya R. YR 2024 SN 1558-1101 K1 Electric potential K1 Nonvolatile memory K1 Computational modeling K1 Computer architecture K1 Logic gates K1 In-memory computing K1 Reliability engineering K1 computing in memory K1 error model K1 gate flips K1 NVM SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.23919/DATE58400.2024.10546875 DO https://doi.org/10.23919/DATE58400.2024.10546875 SF ELIB - SuUB Bremen
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