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1 Ergebnisse
1
JPlace: A Clock-Aware Length-Matching Placement for Rapid S..:
, In:
2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)
,
Chen, Siyan
;
Fu, Rongliang
;
Huang, Junying
... - p. 1-6 , 2024
Link:
https://doi.org/10.23919/DATE58400.2024.10546887
RT T1 <cTitle>2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)</cTitle>: T1 <Title>JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10546887&Exemplar=1&LAN=DE A1 Chen, Siyan A1 Fu, Rongliang A1 Huang, Junying A1 Zhang, Zhimin A1 Ye, Xiaochun A1 Ho, Tsung-Yi A1 Fan, Dongrui YR 2024 SN 1558-1101 K1 Runtime K1 Power demand K1 Superconducting logic circuits K1 Benchmark testing K1 Routing K1 Timing K1 Space exploration K1 superconducting logic K1 RSFQ K1 placement SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.23919/DATE58400.2024.10546887 DO https://doi.org/10.23919/DATE58400.2024.10546887 SF ELIB - SuUB Bremen
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