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1 Ergebnisse
1
The Design of a Low-latency Tensor Decomposition Algorithm ..:
, In:
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Chen, Yu-An
;
Shen, Chung-An
- p. 1-5 , 2024
Link:
https://doi.org/10.1109/ISCAS58744.2024.10557909
RT T1 <cTitle>2024 IEEE International Symposium on Circuits and Systems (ISCAS)</cTitle>: T1 <Title>The Design of a Low-latency Tensor Decomposition Algorithm and VLSI Architecture</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10557909&Exemplar=1&LAN=DE A1 Chen, Yu-An A1 Shen, Chung-An YR 2024 SN 2158-1525 K1 Performance evaluation K1 Tensors K1 Signal processing algorithms K1 Computer architecture K1 Very large scale integration K1 Signal processing K1 Throughput K1 In-band Full Duplex K1 Self-Interference K1 Independent Component Analysis (ICA) SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISCAS58744.2024.10557909 DO https://doi.org/10.1109/ISCAS58744.2024.10557909 SF ELIB - SuUB Bremen
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