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1 Ergebnisse
1
A 28nm Energy-Area-Efficient Row-based pipelined Training A..:
, In:
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Lu, Wei
;
Pei, Han-Hsiang
;
Yu, Jheng-Rong
.. - p. 1-5 , 2024
Link:
https://doi.org/10.1109/ISCAS58744.2024.10558053
RT T1 <cTitle>2024 IEEE International Symposium on Circuits and Systems (ISCAS)</cTitle>: T1 <Title>A 28nm Energy-Area-Efficient Row-based pipelined Training Accelerator with Mixed FXP4/FP16 for On-Device Transfer Learning</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10558053&Exemplar=1&LAN=DE A1 Lu, Wei A1 Pei, Han-Hsiang A1 Yu, Jheng-Rong A1 Chen, Hung-Ming A1 Huang, Po-Tsang YR 2024 SN 2158-1525 K1 Training K1 Quantization (signal) K1 Convolution K1 Transfer learning K1 Pipelines K1 Random access memory K1 CMOS process K1 On-device transfer learning K1 DNN Training accelerator K1 Simulated quantization K1 Frozen weights K1 Multi-bank buffer management SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISCAS58744.2024.10558053 DO https://doi.org/10.1109/ISCAS58744.2024.10558053 SF ELIB - SuUB Bremen
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